In memory devices, each memory cell can store one or more bits of data. A memory cell with two states can store one bit of data per cell, and is referred to as a Single-Level Cell (SLC). A memory cell with four states can store two bits of data per cell, and is referred to as a Multi-Level Cell (MLC). A memory cell with eight states can store three bits of data per cell, and can also be referred to as a MLC or as a Triple-Level Cell (TLC). A memory cell with sixteen states can store four bits of data per cell, and can also be referred to as a MLC or as a Quad-Level Cell (QLC). The MLC memory is advantageous for high device integration. However, as the number of bits programmed in each memory cell increases, the read, write and erase failure rates typically increase.
MLC utilize error correction algorithms to detect and correct errors that occur during operation. Errors can be caused by a number of sources, such as random noise, cell-to-cell interference, read or write disturb, programming error, retention errors, charge leakage and trapping generation. As memory devices continue to be scaled and/or the number of bits stored per cell increases, the error rate tends to increase. Accordingly, there is a continuing need for improved error correction algorithms for use with memory devices.